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TSMC16 PDK + Arm Standard Cell Libraries

This PDK and the 7.5 track standard cell library are fully supported in the Cadre Flow. This process requires additional DRC steps for fill.

Known Issues:

  1. LVS is currently broken for modules

TSMC45 PDK+Libraries

IBM45 PDK+Libraries

Fujitsu55 PDK+Libraries

ASAP7 PDK+Libraries

This kit is partially supported with the following limitations:

  1. Synthesis uses wire length models (WLMs) because there are no TLU+ files included for topographical flow in design compiler
  2. This kit does not yet support verification (DRC/LVS/VCS/Voltus)
  3. This kit does not support chip designs since there are no IO cells included

GPDK45 PDK+Libraries

This kit is partially supported with the following limitations:

  1. Synthesis uses wire length models (WLMs) because there are no TLU+ files included for topographical flow in design compiler
  2. This kit does not yet support verification (DRC/LVS/VCS/Voltus)
  3. This kit does not yet support chip designs
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