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2016

  • "Checkpointing Exascale Memory Systems with Existing Memory Technologies," Nilmini Abeyratne, Hsing-Min Chen, Byoungchan Oh, Ronald Dreslinski, Chaitali Chakrabarti, and Trevor Mudge, Proceedings of the 2016 International Symposium on Memory Systems (MEMSYS), October 2016.
  • "Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes," Yajing Chen, Nikolaos Chiotellis, Li-Xuan Chuo, Carl Pfeiffer, Yao Shi, Ronald G Dreslinski, Anthony Grbic, Trevor Mudge, David D Wentzloff, David Blaauw, and Hun Seok Kim, IEEE Journal on Selected Areas in Communications (JSAC), 2016.
  • "Enhancing DRAM Self-Refresh for Idle Power Reduction," Byoungchan Oh, Nilmini Abeyratne, Jeongseob Ahn, Ronald G. Dreslinski, and Trevor Mudge, Proceedings of the 2016 International Symposium on Low Power Electronics and Design (ISLPED), pages 254-259, August 2016.
  • “Near-threshold Computing in FinFET Technologies: Opportunities for Improved Voltage Scalability,” Nathaniel Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor Mudge, Dennis Sylvester, and David Blaauw, Proceedings of the 53rd Annual Design Automation Conference (DAC), June 2016.
  • “MBus: A System Integration Bus for the Modular Microscale Computing Class,” Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, ZhiYoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, and Prabal Dutta, IEEE Micro (Top Picks), vol. 36, no. 3, Pages 60-70, May-June 2016.
  • “Sirius Implications for Future Warehouse-Scale Computers,” Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ron Dreslinski, Trevor Mudge, Vinicius Petrucci, Lingjia Tang, and Jason Mars, IEEE Micro (Top Picks), vol. 36, no. 3, Pages 42-53, May-June 2016.

  • “Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant,” Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Hailong Yang, Yiping Kang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor Mudge, Vinicius Petrucci, Lingjia Tang, and Jason Mars, ACM Transactions on Computing Systems (TOCS), vol. 34, no. 1, pp. 2:1-2:32, April 2016.

  • “A Low Power Software-Defined-Radio Baseband Processor for the Internet of Things,” Yajing Chen, Shengshuo Lu, Hun-Seok Kim, David Blaauw, Ronald G. Dreslinski, Trevor Mudge, Proceedings of the 22nd International Symposium on High-Performance Computer Architecture (HPCA), March 2016.
  • “Exploring Fine-Grained Heterogeneity with Composite Cores,” Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott Mahlke, IEEE Transactions on Computers (TOC), vol. 65, no. 2, pp. 535-547, February 2016.

2015

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  • “WarpPool: Sharing Requests with Inter-warp Coalescing for Throughput Processors,” John Kloosterman, Jonathan Beaumont, Mick Wollman, Ankit Sethia, Ronald G. Dreslinski, Trevor Mudge, and Scott Mahlke, Proceedings of the 48th International Symposium on Microarchitecture (MICRO), December 2015.
  • “DjiNN and Tonic: DNN As a Service and Its Implications for Future Warehouse Scale Computers,” Johann Hauswald, Yiping Kang, Michael A. Laurenzano, Quan Chen, Cheng Li, Trevor Mudge, Ronald G. Dreslinski, Jason Mars, and Lingjia Tang, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), June 2015.
  • “MBus: An Ultra-low Power Interconnect Bus for Next Generation Nanopower Systems,” Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, ZhiYoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, and Prabal Dutta, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), June 2015. Selected for IEEE Micro Top Picks
  • “A Study of Mobile Device Utilization,” Cao Gao, Anthony Gutierrez, Madhav Rajan, Ronald G. Dreslinski, and Trevor Mudge, Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2015.
  • “The Next-Generation Space Processor (NGSP) Analysis Program: Benchmarking an ARM-Based Heterogeneous Multicore Processor Design for Space Applications,” Jon Ballast, Muhammad Ahmed, Robert Higgins, Warren Snapp, Ronald G. Dreslinski, Trevor Mudge, Mick Wollman, Dong-In Kang, John Walters, and Eric Van Hensbergen, The 40th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2015.
  • “Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers,” Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ron Dreslinski, Trevor Mudge, Vinicius Petrucci, Lingjia Tang, and Jason Mars,  Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015, Pages 223-238. Selected for IEEE Micro Top Picks
  • “Adrenaline: Pinpointing and Reining in Tail Queries with Quick Voltage Boosting,” Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas Wenisch, Jason Mars, Lingjia Tang, and Ronald G. Dreslinski, Proceedings of the 21st International Symposium on High-Performance Computer Architecture (HPCA), February 2015.

2014

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  • “Using Graphics Processing Units in an LTE Base Station”, Qi Zheng, Yajing Chen, Hyunseok Lee, Ronald Dreslinski, Chaitali Chakrabarti, Achilles Anastasopoulos, Scott Mahlke, and Trevor Mudge, Journal of Signal Processing Systems (JSPS), Pages 1-13. 2014.
  • “Hi-Rise: A High-Radix Switch for 3D Integration with Single-cycle Arbitration”, Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor Mudge, and David Blaauw, Proceedings of the 47th International Symposium on Microarchitecture (MICRO), December 2014.    
  • “Heterogeneous microarchitectures trump voltage scaling for low-power cores”, Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald Dreslinski, Thomas F. Wenisch, and Scott Mahlke, Proceedings of the 23rd International Conference on Parallel Architectures and Compilation (PACT), August 2014, Pages 237-250.
  • “Evaluating Private vs. Shared Last-Level Caches for Energy Efficiency in Asymmetric Multi-Cores”, Anthony Gutierrez, Ronald G. Dreslinski, and Trevor Mudge, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), July 2014.
  • “Quality-of-Service for a High-Radix Switch”, Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, Reetuparna Das, Ronald Dreslinski, David Blaauw, and Trevor Mudge, Proceedings of the 51st Annual Design Automation Conference (DAC), June 2014.
  • “VIX: Virtual Input Crossbars for Efficient Switch Allocation”, Supriya Rao, Reetuparna Das, Supreet Jeloka, David Blaauw, Ronald Dreslinski, and Trevor Mudge, Proceedings of the 51st Annual Design Automation Conference (DAC), June 2014.
  • “A Hybrid Approach to Offloading Mobile Image Classification”, Johann Hauswald, Thomas Manville, Qi Zheng, Ronald Dreslinski, Chaitali Chakrabarti, and Trevor Mudge, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2014, Pages 8375-8379.
  • “An Architecture for Low-Power High-Performance Embedded Computing”, Ronald G. Dreslinski, Qi Zheng, Robert P. Higgins, Johann Hauswald, David Blaauw, Trevor Mudge, Chaitali Chakrabarti, Jon Ballast, and Warren Snapp, The 39th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), April 2014.
  • “Sources of Error in Full System Simulation”, Anthony Gutierrez, Joseph Pusdesris, Ronald Dreslinski, and Trevor Mudge, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014, Pages 13-22. Best Paper Award
  • “A Study of Thread Level Parallelism on Mobile Devices”, Cao Gao, Anthony Gutierrez, Ronald G. Dreslinski, Trevor Mudge, Kristian Flautner, and Geoffrey Blake, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014, Pages 126-127.
  • “Integrated 3D-Stacked Server Designs for Increasing Physical Density of Key-Value Stores”, Anthony Gutierrez, Michael Cieslak, Bharan Giridhar, Ronald Dreslinski, Luis Ceze, and Trevor Mudge, Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2014, Pages 485-498.

2013

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  • “Parallelism and Boosting Limits of Dim Silicon”, Nathaniel Pinckney, Ronald G. Dreslinski, Korey Sewell, David Fick, Trevor Mudge, Dennis Sylvester, and David Blaauw, IEEE Micro, Sept.-Oct. 2013, Vol. 33, No. 5, Pages 30-37. 
  • “Centip3De: A Many-Core Prototype Exploring 3D Integration and Near-Threshold Computing”, Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Dennis Sylvester, David Blaauw, and Trevor Mudge, Communications of the ACM, Vol. 56 No. 11, Pages 97-104, November 2013.
  • “Centip3De: A 64-Core, 3D Stacked Near-Threshold System”, Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Dennis Sylvester, David Blaauw, and Trevor Mudge, IEEE Micro, Vol. 33, No.2, Pages 8-16, March- April 2013.
  • “Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS”, David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Trevor Mudge, Dennis Sylvester, and David Blaauw, IEEE Journal of Solid State Circuits (JSSC), Vol. 48, No. 1, January 2013, Pages 104-117. 
  • “Exploring DRAM Organizations for Energy-Efficient and Resilient Exascale Memories”, Bharan Giridhar, Michael Cieslak, Deepankar Duggal, Ronald Dreslinski, Hsing Min Chen, Robbert Patti, Betina Hold, Chaitali Chakrabarti, Trevor Mudge, and David Blaauw, Proceedings of SC13: International Conference for High Performance Computing, Networking, Storage and Analysis (SC), November 2013, Article No. 23, 12 Pages. 
  • “Architecting an LTE Base Station with Graphics Processing Units”, Qi Zheng, Yajing Chen, Ronald Dreslinski, Chaitali Chakrabarti, Achilles Anastasopoulos, Scott Mahlke, and Trevor Mudge, 2013 IEEE Workshop on Signal Processing Systems (SiPS), October 2013, Pages 219-224. Selected to appear in the Journal of Signal Processing Systems (JSPS)
  • “WiBench: An Open Source Kernel Suite for Benchmarking Wireless Systems”, Qi Zhang, Yajing Chen, Ronald Dreslinski, Chaitali Chakrabarti, Achilles Anastasopoulos, Scott Mahlke, and Trevor Mudge, IEEE International Symposium on Workload Characterization (IISWC), September 2013, Pages 123-132.
  • “Hardware Acceleration for Similarity Measurement in Natural Language Processing”, Prateek Tandon, Jichaun Chang, Ronald G. Dreslinski, V. Qazvinian, Partha Ranganathan, and Thomas F. Wenisch, International Symposium on Low Power Electronic Design (ISLPED), September 2013, Pages 409-414.
  • “Catnap: Energy Proportional Multiple Network-on-Chip”, Reetuparna Das, Satish Narayanasamy, Sudhir K. Satpathy, and Ronald Dreslinski, Proceedings of the 40th International Symposium on Computer Architecture (ISCA), June 2013, Pages 320-331.   
  • “Parallelization Techniques for Implementing Trellis Algorithms on Graphics Processors", Qi Zheng, Yajing Chen, Ronald Dreslinski, Chaitali Chakrabarti, Achilles Anastasopoulos, Scott Mahlke, and Trevor Mudge, IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, Pages 1220-1223.
  • “Scaling Towards Kilo-Core Processors with Asymmetric High Radix Topologies”, Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald Dreslinski, David Blaauw, and Trevor Mudge, Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), February 2013, Pages 496-507.

2012

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  • “Swizzle-Switch Networks for Many-Core Systems”, Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas Wenish, Dennis Sylvester, David Blaauw, and Trevor Mudge, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 2, No. 2, Pages 278-294, June 2012.  
  • “Composite Cores: Pushing Heterogeneity into a Core”, Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald Dreslinski, Thomas F. Wenisch, and Scott Mahlke, Proceedings of the 45th International Symposium on Microarchitecture (MICRO), December 2012, Pages 317-328. 
  • “Embedded Way Prediction for Last-Level Caches”, Faisal Sleiman, Ronald Dreslinski, and Thomas Wenisch, Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), October 2012, Pages 167-174.   
  • “Lazy Cache Invalidation for Self-Modifying Codes”, Anthony Gutierrez, Joseph Pusdesris, Ronald G. Dreslinski, and Trevor Mudge, The International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2012, Pages 151-160. 
  • “XPoint Cache: Scaling Existing Bus-based Coherence Protocols for 2D and 3D Many-core Systems”, Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Pinckney, Sudhir Satpathy, David Blaauw, Dennis Sylvester, and Trevor Mudge, Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), August 2012, Pages 75-86. 
  • "Centip3De: A 64-Core, 3D Stacked, Near-Threshold System”, Ronald Dreslinski, David Fick, Bharan Giridhar, G. Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyoung Lee, D. Kim, N. Liu, Michael Wieckowski, Gregory Chen, Trevor Mudge, Dennis Sylvester and David Blaauw, Proceedings of the 24th Hot Chips: A Symposium on High Performance Chips (HotChips), August 2012, Pages 400-430.
    • Selected for IEEE MIcro Special Edition on HotChips
    • Selected for Communications of the ACM Research Highlight
  • “Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems”, Ronald Dreslinski, Korey Sewell, Sudhir Satpathy, Thomas Manville, Nathaniel Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas Wenisch, Dennis Sylvester, David Blaauw, and Trevor Mudge, Proceedings of the 24th Hot Chips: A Symposium on High Performance Chips (HotChips), August 2012, Pages 112-155. 
  • “High Radix Self-Arbitrating Switch Fabric with Multiple Arbitration Schemes and Quality of Service”, Sudhir K. Satpathy, Reetuparna Das, Ronald Dreslinski, Trevor Mudge, Dennis Sylvester, and David Blaauw, Proceedings of the 49th Annual Design Automation Conference (DAC), June 2012, Pages 406-411. 
  • “Process Variation in Near-Threshold Wide SIMD Architectures”, Sangwon Seo, Ronald Dreslinski, Mark Who, Y. Park, Scott Mahlke, David Blaauw, Chaitali Chakrabarti, and Trevor Mudge, Proceedings of the 49th Design Automation Conference (DAC), June 2012, Pages 980-987. 
  • “Assessing the Performance Limits of Parallelized Near-Threshold Computing”, Nathaniel Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Dennis Sylvester, Trevor Mudge, and David Blaauw, Proceedings of the 49th Design Automation Conference (DAC), June 2012, Pages 1147-1152. 
  • “Centip3De: A 3930 DMIPS/W Configurable Near-Threshold 3D Stacked System With 64 ARM Cortex-M3 Cores”, David Fick, Ronald G. Dreslinski, Bahran Giridhar, Gouho Kim, Sangwon Seo, Matt Fojtik, Sudhir Satpathy, Yoomyoung Lee, Dayeon Kim, Normanrach Liu, Michael Weikowski, Gregory Chen, Trevor Mudge, Dennis Sylvester, and David Blaauw, IEEE International Solid-State Circuits Conference (ISSCC), February 2012, Pages 190-192. Selected to appear in Journal of Solid State Circuits (JSSC)
  • “A 4.5Tb/s 3.4Tb/s/W 64×64 Switch Fabric with Self-Updating Least Recently Granted Priority and Quality of Service Arbitration in 45nm CMOS”, Sudhir Satpathy, Korey Sewell, Thomas Manville, Y. Chen, Ronald G. Dreslinski, Dennis Sylvester, Trevor Mudge, and David Blaauw, IEEE International Solid-State Circuits Conference (ISSCC), February 2012, Pages 478-480.

2011

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  • “Full-System Analysis and Characterization of Interactive Smartphone Applications”, Anthony Gutierrez, Ronald Dreslinski, Thomas Wenisch, Trevor Mudge, Ali Saidi, Chris Emmons, and Nigel Paver, IEEE International Symposium on Workload Characterization (IISWC), November 2011, Pages 81-90. 
  • “SWIFT: A 2.1Tb/s 32x32 Self-Arbitrating Manycore Interconnect Fabric”, Sudhir Satpathy, Ronald G. Dreslinski, Taichuan Ou, Dennis Sylvester, Trevor Mudge, and David Blaauw, IEEE Symposium on VLSI Technology and Circuits (VLSIC), June 2011, Pages 138- 139. 
  • “Low Power Interconnects for SIMD Computers”, Mark Woh, Sudhir Satpathy, Ronald G. Dreslinski, Daniel Kershaw, Dennis Sylvester, David Blaauw, and Trevor Mudge, Proceedings Design, Automation and Test in Europe (DATE), March 2011, Pages 600-605. 
  • “Bloom Filter Guided Transaction Scheduling”, Geoffrey Blake, Ronald G. Dreslinski, and Trevor Mudge, Proceedings 17th International Symposium on High-Performance Computer Architecture (HPCA), February 2011, Pages 75-86. 

2010

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  • “Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits”, Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge, Proceedings of the IEEE, Vol. 98, No. 2, Pages 253-266, February 2010.
  • “Diet SODA: A Power Efficient Processor for Digital Cameras”, Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott Mahlke, and Trevor Mudge, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), August 2010, Pages 79-84.
  • “Evolution of Thread Level Parallelism in Desktop Applications", Geoffrey Blake, Ronald G. Dreslinski, Trevor Mudge, and Krisztian Flautner, The 37th International Symposium on Computer Architecture (ISCA), June 2010, Pages 302-313.
  • “A 1.07 Tbit/s 128x128 swizzle network for SIMD processors”, Sudhir Satpathy, Zhiyong Foo, Bahran Giridhar, Ronald G. Dreslinski, Dennis Sylvester, Trevor Mudge, and David Blaauw, IEEE Symposium on VLSI Circuits (VLSIC), June 2010, Pages 81-82.
  • “Circuit Design Advances for Ultra-Low Power Sensing Platforms”, Michael Wieckowski, Ronald G. Dreslinski, Trevor Mudge, David Blaauw, and Dennis Sylvester, Proceedings of the International Society for Optics and Photonics (SPIE), Vol. 7679, 76790W (2010).

Earlier than 2010

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  • “A Survey of Multicore Architectures”, Geoffrey Blake, Ronald G. Dreslinski, and Trevor Mudge, IEEE Signal Processing Magazine, Vol. 26, No. 6, Pages 26-37, November 2009. 

  • “Proactive Transaction Scheduling for Contention Management”, Geoffrey Blake, Ronald G. Dreslinski, and Trevor Mudge, The 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2009, Pages 156-167.

  • “Reconfigurable Energy Efficient Near Threshold Cache Architectures”, Ronald G. Dreslinski, Gregory Chen, Trevor Mudge, David Blaauw, Dennis Sylvester, and Krisztian Flautner, The 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), November 2008, Pages 459-470.  
  • “Energy Efficient Near-threshold Chip Multi-processing”, Bo Zhai, Ronald G. Dreslinski, Dennis Sylvester, Trevor Mudge, and David Blaauw, International Symposium on Low Power Electronic Design (ISLPED), August 2007, Pages 32-37.  Best Paper Nominee
  •  “An Energy Efficient Architecture Using Near Threshold Operation”, Ronald G. Dreslinski, Bo Zhai, Trevor Mudge, David Blaauw, and Dennis Sylvester, The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007, Pages 175-188.

  • “Analysis of Hardware Prefetching Across Virtual Page Boundaries”, Ronald G. Dreslinski, Ali Saidi, Trevor Mudge, and Steven K. Reinhardt, Proceedings of the 4th International Conference on Computing Frontiers, May 2007, Pages 13-22.  

  • “The M5 Simulator: Modeling Networked Systems", Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi, and Steven K. Reinhardt, IEEE Micro, Vol. 26, No. 4, Pages 52-60, July/August 2006.

  • “PicoServer: Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor”, Taeho Kgil, Shaun D’Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Steven K. Reinhardt, Krisztian Flautner, and Trevor Mudge, 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006, Pages 117-128. 
  • “Performance Analysis of System Overheads in TCP/IP Workloads”, Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, and Steven K. Reinhardt, Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2005, Pages 218-228.

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